An FPGA Architecture for the RRT Algorithm Based on Membrane Computing

This paper investigates an FPGA architecture whose primary function is to accelerate parallel computations involved in the rapid-exploring random tree (RRT) algorithm. The RRT algorithm inherently serial, while each computing step there are many that can be executed simultaneously. Nevertheless, how carry out these on so a high degree of acceleration realized key issue. Membrane paradigm inspired from structures and functions eukaryotic cells. As newly proposed membrane model, generalized numerical P system (GNPS) intrinsically parallel; so, it good candidate for modeling Open problems implementation GNPS include: (1) whether possible model with GNPS; (2) if yes, design such achieve better speedup; (3) instead implementing GNPSs fixed-point-number format, devise working floating-point-number format. In this paper, we modeled at first, showing feasible GNPS. An was fabricated according GNPS-modeled RRT. architecture, computations, which parallel, accommodated different inner membranes These designed as Verilog modules register transfer level model. All within triggered by same clock impulse implement computing. validated Xilinx VC707 evaluation board. Compared software simulation RRT, achieves speedup 104 order magnitude. Although obtained small map, reveals promises higher compared previously reported architectures.